Reservoir capacitor of semiconductor device and method for fabricating the same

ABSTRACT

A method for fabricating a reservoir capacitor of a semiconductor device where a first peripheral circuit region and a second peripheral circuit region are defined comprises: forming a gate on an upper portion of a semiconductor substrate of the second peripheral circuit region; forming an interlayer insulating film on the entire upper portion of the semiconductor substrate including the gate; etching the interlayer insulating film of the second peripheral circuit region to form a bit line contact hole; forming a bit line material and a sacrificial film on the upper portion of the interlayer insulating film including the bit line contact hole; and etching the sacrificial film of the first peripheral circuit region to form a trench that exposes the bit line material.

CROSS-REFERENCE TO RELATED APPLICATION

The priority of Korean patent application No. 10-2009-0113626 filed onNov. 24, 2009, the disclosure of which is hereby incorporated in itsentirety by reference, is claimed.

BACKGROUND OF THE INVENTION

An embodiment of the present invention relates to a reservoir capacitorof a semiconductor device and a method for fabricating the same, andmore specifically, to a reservoir capacitor formed when a buried gateprocess is applied.

In general, a semiconductor device such as a Dynamic Random AccessMemory (DRAM) comprises various micro-sized elements. In order tooperate these micro-sized elements, the semiconductor device generatesan internal voltage.

Meanwhile, the use of the internal voltage can generate noise, therebydestabilizing a voltage level. In order to inhibit the generation ofnoise, a reservoir capacitor having a large capacitance is fabricated.The reservoir capacitor is located in a peripheral circuit region wheremicro-sized elements are formed.

However, in the current buried gate, a storage node contact of a cellregion is formed before a bit line pad of a peripheral circuit region isformed. That is, a gate of the cell region, the gate of the peripheralcircuit region, a bit line of the cell region and the bit line pad ofthe peripheral circuit region are formed to have different heights.

As a result, the storage node contact of the cell region and the gatematerial of the peripheral circuit region, that is, a MOS capacitor, areformed to have the same height. When the reservoir capacitor is formedusing the storage node contact, the storage node contact is formed inthe MOS capacitor of the existing peripheral circuit region, so that theMOS capacitor and the reservoir capacitor cannot be used simultaneously.

BRIEF SUMMARY OF THE INVENTION

Various embodiments of the invention are directed to using a Metal OxideSemiconductor (MOS) capacitor and a reservoir capacitor simultaneouslywhen a buried gate of a cell region is applied.

According to an embodiment of the present invention, a method forfabricating a semiconductor device, the method comprising: asemiconductor substrate including a first peripheral circuit region anda second peripheral circuit region; forming a gate over a semiconductorsubstrate in the second peripheral circuit region; forming an interlayerinsulating film on the entire the semiconductor device including thegate; etching the interlayer insulating film in the second peripheralcircuit region to form a bit line contact hole; forming a bit linematerial and a sacrificial film over the interlayer insulating filmincluding the bit line contact hole; and etching the sacrificial film inthe first peripheral circuit region to form a trench in the firstperipheral circuit region, the trench exposing the bit line material.

Further comprising: forming a gate material in the first peripheralcircuit region while the gate is being formed in the second peripheralcircuit region. The gate material in the first peripheral circuit regionforms of a Metal oxide Semiconductor (MOS) capacitor.

Further comprising patterning the bit line material in the secondperipheral circuit region to form a bit line pad. The bit line materialhas a stack structure including a barrier metal layer, a tungsten layerand a hard mask nitride film. The trench defines a reservoir capacitorregion. Further comprising forming a conductive layer in the trench toform a reservoir capacitor.

According to another embodiment of the present invention A method forfabricating a semiconductor device, the method comprising: asemiconductor substrate including a cell region, a first peripheralcircuit region and a second peripheral circuit region; forming a buriedcell gate and landing plug contact in the semiconductor substrate in thecell region; forming a gate material over the semiconductor substrate inthe first and second peripheral circuit regions; patterning the gatematerial in the second peripheral circuit region to form a peri-gate;forming a storage node contact and a bit line in the cell region each ofwhich is electrically coupled with the landing plug contact in the cellregion; forming an interlayer insulating film over the semiconductorsubstrate including the bit line and the storage node contact of thecell region, over the gate material of the first peripheral circuitregion and over the semiconductor substrate including the peri-gate inthe second peripheral circuit region; etching the interlayer insulatingfilm to form a peri-bit line contact hole exposing the peri-gate;forming a bit line material in the peri-bit line contact hole over thesemiconductor substrate in the first peripheral circuit region;patterning the bit line material in the second peripheral circuit regionto form a bit line pad; forming a sacrificial film over the interlayerinsulating film in the cell region, over the bit line material in thefirst peripheral circuit region and over the bit line pad in the secondperipheral circuit region; and etching the sacrificial film in the firstperipheral circuit region and in the cell region to form a cell trenchexposing the storage node contact in the cell region and form aperi-trench exposing the bit line material in the first peripheralcircuit region.

The gate material in the first peripheral circuit region defines part ofa MOS capacitor. The bit line material has a stack structure including abarrier metal layer, a tungsten layer and a hard mask nitride film.

The cell trench formed in the cell region defines a storage node region.The peri trench formed in the first peripheral circuit region defines areservoir capacitor region.

Further comprising forming a conductive layer in the cell trench andperi trench to form a storage node, thereby forming a reservoircapacitor.

According to an embodiment of the present invention, A reservoircapacitor of a semiconductor device, the reservoir capacitor comprising:a semiconductor substrate comprising a first peripheral circuit regionand a second peripheral circuit region; a gate formed over thesemiconductor substrate in the second peripheral circuit region; a bitline pad formed over the gate to be electrically coupled to the gate; abit line material formed in the first peripheral circuit region of thesame layer as the bit line pad; and a trench formed to exposed the bitline material in the first peripheral circuit region. The trench formedin the first peripheral circuit region defines a reservoir capacitorregion.

Further comprising a MOS capacitor formed under the trench in the firstperipheral circuit region, wherein the MOS capacitor is formed of thesame material as the gate. The gate in the second peripheral circuitregion and the MOS capacitor in the first peripheral circuit region hasa deposition structure including a gate oxide, a gate poly silicon and ahard mask.

Further comprising forming a conductive layer in the trench. The bitline pad has a deposition structure including a barrier metal layer, atungsten layer and a hard mask nitride film.

According to an embodiment of the present invention, a semiconductordevice comprises: a first peripheral circuit region and a secondperipheral circuit region, wherein the first peripheral circuit regioncomprises: a metal-oxide-semiconductor (MOS) capacitor pattern formedover a substrate; and a reservoir capacitor pattern formed over the MOScapacitor pattern, and wherein the second peripheral circuit regioncomprises: a gate formed over the substrate; and a bit line pad formedover the gate to be electrically coupled to the gate, and wherein thereservoir capacitor pad is formed at the substantially same level as thebit line pad formed in the second peripheral circuit region.

The reservoir capacitor pad is formed of the same material as the bitline pad. The reservoir capacitor pad and the bit line pad are formedsimultaneously at the same processing step.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 a to 1 h are cross-sectional diagrams illustrating a reservoircapacitor of a semiconductor device and a method for fabricating thesame according to an embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

The present invention will be described in detail with reference to theattached drawings.

FIGS. 1 a to 1 h are cross-sectional diagrams illustrating a reservoircapacitor of a semiconductor device and a method for fabricating thesame according to an embodiment of the present invention. Views (I),(II) and (III) show a cell region, a first peripheral circuit regionwhere a reservoir capacitor is formed, and a second peripheral circuitregion, respectively. In this embodiment, the method for fabricating areservoir capacitor can increase the efficiency by using a process forforming a gate, a bit line and a capacitor in the cell region.

Referring to FIG. 1 a, a device isolation film 105 is formed in asemiconductor substrate 100, and a buried gate 117 is formed in thesemiconductor substrate 100 of the cell region (I). A landing plug 120is formed in the semiconductor substrate 100 between the buried gates117. After the semiconductor substrate 100 is etched to form a recess,the recess is filled with a tungsten layer 110 and a nitride film 115,thereby forming the buried gate 117.

On the upper portion of the semiconductor substrate 100 of the firstperipheral circuit region (II) and the second peripheral circuit region(III) except the cell region (I), a deposition structure including agate oxide film (not shown), a gate polysilicon layer 125, a gate metallayer 130 and a gate hard mask layer 135 are formed. The gate metallayer 130 includes a tungsten layer. The gate hard mask layer 135includes a nitride film. The gate hard mask layer 135 is formed to havea thickness ranging from 500 to 700 Å.

The deposition structure of the second peripheral circuit region (III)is patterned to form a gate pattern. A spacer 137 is formed at sidewallsof the gate pattern to form a gate 141.

The deposition structure formed in the first peripheral circuit region(II) is not patterned. The deposition structure is used as a Metal OxideSemiconductor (MOS) capacitor.

After a first mask pattern (not shown) that opens the cell region (I) isformed, a first interlayer insulating film 140 is formed only on theupper portion of the cell region (I). The first interlayer insulatingfilm 140 is etched to form a bit line region (not shown) and a storagenode contact hole that exposes the landing plug 120.

The storage node contact hole is filled with a polysilicon layer to forma storage node contact 143. A barrier metal layer 148 is deposited onthe inside wall of the bit line region (not shown), and the bit lineregion is filled with the tungsten layer 145 and the hard mask nitridefilm 147, thereby forming a bit line 149. The hard mask nitride film 147is formed to have a thickness ranging from 500 to 700 Å. The first maskpattern (not shown) that opens the cell region (I) is removed.

A second interlayer insulating film 150 is formed on the upper portionof the semiconductor substrate 100 including the first interlayerinsulating film 140 of the cell region (I) where the bit line 149 andthe storage node contact 143 are interposed, the gate hard mask layer135 of the first peripheral circuit region (II) and the gate 141 of thesecond peripheral circuit region (III). The second interlayer insulatingfilm 150 is formed with a material including an oxide film to have athickness ranging from 300 to 400 Å.

Referring to FIG. 1 b, a second mask pattern (not shown) that opens thesecond peripheral circuit region (III) is formed. A bit line contacthole 160 is formed in the second peripheral circuit region (III). Thebit line contact hole 160 is obtained by etching a portion of the secondinterlayer insulating film 150, the gate hard mask layer 135 and Thegate metal layer 130 to expose the gate metal layer 130. The secondinterlayer insulating film 150 adjacent to the gate 141 may be etched toexpose the semiconductor substrate 100.

The second mask pattern (not shown) that opens the second peripheralcircuit region (III) is removed.

Referring to FIG. 1 c, a barrier metal layer 165 and a tungsten layer170 are deposited on the cell region (I), on the upper portion of thesecond interlayer insulating film 150 of the first peripheral circuitregion (II) and on the upper portion of the second interlayer insulatingfilm 150 including the bit line contact hole 160 of the secondperipheral circuit region (III). After the tungsten layer 170 is formedto have a thickness ranging from 700 to 1000 Å, a Chemical MechanicalPolishing (CMP) process is performed so that the remaining tungstenlayer 170 has a thickness ranging from 300 to 600 Å.

Referring to FIG. 1 d, the tungsten layer 170 and the barrier metallayer 165 of the second peripheral circuit region (III) are patterned toform a bit line pad 173. The tungsten layer 170 and the barrier metallayer 165 of the cell region (I) are removed, and the tungsten layer 170and the barrier metal layer 165 of the first peripheral circuit region(II) remain.

Referring to FIG. 1 e, the second interlayer insulating film 150 of thecell region (I) is removed.

Referring to FIG. 1 f, an etch barrier film 175 is deposited on theupper portion of the first interlayer insulating film 140 including thestorage node contact 143 and the bit line 149 of the cell region (I), onthe upper portion of the tungsten layer 170 of the first peripheralcircuit region (II), and on the upper portion of the first interlayerinsulating film 150 including the bit line pad 173 of the secondperipheral circuit region (III). The etch barrier film 175 is depositedin order to form a reservoir capacitor of the first peripheral circuitregion (II), and is formed with a is material including a nitride filmto have a thickness ranging from 500 to 600 Å.

Even when an overlay between the storage node contact 143 and thestorage node region of the cell region (I) is dislocated, the thicknessof the combined etch barrier film 175 and the hard mask nitride film 147of the bit line 149 ranges from 1000 to 1300 Å, so that an electricshort does not occur between the storage node of the cell region (I) andthe bit line 149 of the cell region (I).

Referring to FIG. 1 f, a first sacrificial film 180 and a secondsacrificial film 185 are formed on the upper portion of the etch barrierfilms 175 in the cell region (I), the first peripheral circuit region(II) and the second peripheral circuit region (III). The firstsacrificial film 180 and the second sacrificial film 185 are formed withmaterial including an oxide film, more preferably, a Phosphors SilicateGlass (PSG) oxide film and TetraEthOxySilane (TEOS) oxide film,respectively.

Referring to FIG. 1 g, the second sacrificial film 185, the firstsacrificial film 180 and the etch barrier film 175 of the cell region(I) are etched to form a storage node region 190 that exposes thestorage node contact 143. In the etching process of the storage noderegion 190 of the cell region (I), the second sacrificial film 185, thefirst sacrificial film 180 and the etch barrier film 175 of the firstperipheral circuit region (II) are simultaneously etched to form areservoir capacitor region 195 that exposes the tungsten layer 170.

Referring to FIG. 1 h, a subsequent process for depositing a conductivelayer 197 is performed in the storage node region 190 of the cell region(I) and the reservoir capacitor region 195 of the first peripheralcircuit region (II). As a result, a storage node is formed in the cellregion (I), and a reservoir capacitor is formed in the first peripheralcircuit region (II).

As described above, a reservoir capacitor using a bit line pad is formedso that a MOS capacitor and a reservoir capacitor can be usedsimultaneously.

The reservoir capacitor is not limited in the method shown in FIGS. 1 ato 1 h.

The reservoir capacitor of the semiconductor device is described withreference to FIG. 1 h. Here, the cell region is not described, but onlythe peripheral circuit regions where a MOS capacitor and a reservoircapacitor are formed are described.

The semiconductor substrate 100 is prepared where the first peripheralcircuit region (II) where the reservoir capacitor is formed and thesecond peripheral circuit region (III) are defined. The gate 141 isdisposed on the upper portion of the semiconductor substrate 100 of thesecond peripheral circuit region (III). The gate 141 has a depositionstructure including the gate oxide film (not shown), the gatepolysilicon layer 125, the gate metal layer 130 and the gate hard masklayer 135. The spacer 137 is disposed at sidewalls of the depositionstructure. The deposition structure is not patterned but remains in thefirst peripheral circuit region (II). The deposition structure is usedas a Metal Oxide Semiconductor (MOS) capacitor.

The bit line pad 173 is disposed on the upper portion of the gate 141 ofthe second peripheral circuit region (III). The bit line pad 173 iscoupled to the gate 141 or to the semiconductor substrate 100. The bitline pad 173 includes the barrier metal layer 165 and the tungsten layer170. Also, the barrier metal layer 165 and the tungsten layer 170 aredisposed in the first peripheral circuit region (II).

The reservoir capacitor region 195 that exposes the tungsten layer 170is located in the first peripheral circuit region (II). As a result, thereservoir capacitor including the conductive layer 197 is disposed inthe reservoir capacitor region 195.

As described above, the reservoir capacitor according to an embodimentof the present invention is fabricated while the bit line pad 173 isformed. Thus, the reservoir capacitor is formed independently from thestep of forming the MOS capacitor located under the reservoir capacitor.As a result, both of the MOS capacitor and the reservoir capacitor canbe formed.

The above embodiments of the present invention are illustrative and notlimitative. Various alternatives and equivalents are possible. Theinvention is not limited by the type of deposition, etching polishing,and patterning steps describe herein. Nor is the invention limited toany specific type of semiconductor device. For example, the presentinvention may be implemented in a dynamic random access memory (DRAM)device or non volatile memory device. Other additions, subtractions, ormodifications are obvious in view of the present disclosure and areintended to fall within the scope of the appended claims.

1. A method for fabricating a semiconductor device, the methodcomprising: providing a semiconductor substrate including a firstperipheral circuit region and a second peripheral circuit region;forming a gate over a semiconductor substrate in the second peripheralcircuit region; forming an interlayer insulating film on the entire thesemiconductor device including the gate; etching the interlayerinsulating film in the second peripheral circuit region to form a bitline contact hole; forming a bit line material and a sacrificial filmover the interlayer insulating film including the bit line contact hole;and etching the sacrificial film in the first peripheral circuit regionto form a trench in the first peripheral circuit region, the trenchexposing the bit line material.
 2. The method according to claim 1,further comprising: forming a gate material in the first peripheralcircuit region while the gate is being formed in the second peripheralcircuit region.
 3. The method according to claim 2, wherein the gatematerial in the first peripheral circuit region forms of a Metal oxideSemiconductor (MOS) capacitor.
 4. The method according to claim 1,further comprising patterning the bit line material in the secondperipheral circuit region to form a bit line pad.
 5. The methodaccording to claim 1, wherein the bit line material has a stackstructure including a barrier metal layer, a tungsten layer and a hardmask nitride film.
 6. The method according to claim 1, wherein thetrench defines a reservoir capacitor region.
 7. The method according toclaim 1, further comprising forming a conductive layer in the trench toform a reservoir capacitor.
 8. A method for fabricating a semiconductordevice, the method comprising: providing a semiconductor substrateincluding a cell region, a first peripheral circuit region and a secondperipheral circuit region; forming a buried cell gate and landing plugcontact in the semiconductor substrate in the cell region; forming agate material over the semiconductor substrate in the first and secondperipheral circuit regions; patterning the gate material in the secondperipheral circuit region to form a peri-gate; forming a storage nodecontact and a bit line in the cell region each of which is electricallycoupled with the landing plug contact in the cell region; forming aninterlayer insulating film over the semiconductor substrate includingthe bit line and the storage node contact of the cell region, over thegate material of the first peripheral circuit region and over thesemiconductor substrate including the peri-gate in the second peripheralcircuit region; etching the interlayer insulating film to form aperi-bit line contact hole exposing the peri-gate; forming a bit linematerial in the peri-bit line contact hole over the semiconductorsubstrate in the first peripheral circuit region; patterning the bitline material in the second peripheral circuit region to form a bit linepad; forming a sacrificial film over the interlayer insulating film inthe cell region, over the bit line material in the first peripheralcircuit region and over the bit line pad in the second peripheralcircuit region; and etching the sacrificial film in the first peripheralcircuit region and in the cell region to form a cell trench exposing thestorage node contact in the cell region and form a peri-trench exposingthe bit line material in the first peripheral circuit region.
 9. Themethod according to claim 8, wherein the gate material in the firstperipheral circuit region defines part of a MOS capacitor.
 10. Themethod according to claim 8, wherein the bit line material has a stackstructure including a barrier metal layer, a tungsten layer and a hardmask nitride film.
 11. The method according to claim 8, wherein the celltrench formed in the cell region defines a storage node region.
 12. Themethod according to claim 8, wherein the peri trench formed in the firstperipheral circuit region defines a reservoir capacitor region.
 13. Themethod according to claim 8, further comprising forming a conductivelayer in the cell trench and peri trench to form a storage node, therebyforming a reservoir capacitor.
 14. A reservoir capacitor of asemiconductor device, the reservoir capacitor comprising: asemiconductor substrate comprising a first peripheral circuit region anda second peripheral circuit region; a gate formed over the semiconductorsubstrate in the second peripheral circuit region; a bit line pad formedover the gate to be electrically coupled to the gate; a bit linematerial formed in the first peripheral circuit region of the same layeras the bit line pad; and a trench formed to exposed the bit linematerial in the first peripheral circuit region.
 15. The reservoircapacitor according to claim 14, wherein the trench formed in the firstperipheral circuit region defines a reservoir capacitor region.
 16. Thereservoir capacitor according to claim 14, further comprising a MOScapacitor formed under the trench in the first peripheral circuitregion, wherein the MOS capacitor is formed of the same material as thegate.
 17. The reservoir capacitor according to claim 16, wherein thegate in the second peripheral circuit region and the MOS capacitor inthe first peripheral circuit region has a deposition structure includinga gate oxide, a gate poly silicon and a hard mask.
 18. The reservoircapacitor according to claim 14, further comprising forming a conductivelayer in the trench.
 19. The reservoir capacitor according to claim 14,wherein the bit line pad has a deposition structure including a barriermetal layer, a tungsten layer and a hard mask nitride film.
 20. Asemiconductor device comprising: a first peripheral circuit region and asecond peripheral circuit region, wherein the first peripheral circuitregion comprises: a metal-oxide-semiconductor (MOS) capacitor patternformed over a substrate; and a reservoir capacitor pattern formed overthe MOS capacitor pattern, and wherein the second peripheral circuitregion comprises: a gate formed over the substrate; and a bit line padformed over the gate to be electrically coupled to the gate, and whereinthe reservoir capacitor pad is formed at the substantially same level asthe bit line pad formed in the second peripheral circuit region.